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x86 Assembly Language Reference Manual Oracle Solaris 11.1 Information Library |
1. Overview of the Oracle Solaris x86 Assembler
2. Oracle Solaris x86 Assembly Language Syntax
Binary Arithmetic Instructions
Decimal Arithmetic Instructions
Flag Control (EFLAG) Instructions
Data Transfer Instructions (Floating Point)
Basic Arithmetic Instructions (Floating-Point)
Comparison Instructions (Floating-Point)
Transcendental Instructions (Floating-Point)
Load Constants (Floating-Point) Instructions
Control Instructions (Floating-Point)
SIMD State Management Instructions
Data Transfer Instructions (MMX)
Packed Arithmetic Instructions (MMX)
SIMD Single-Precision Floating-Point Instructions (SSE)
Data Transfer Instructions (SSE)
Packed Arithmetic Instructions (SSE)
Shuffle and Unpack Instructions (SSE)
MXCSR State Management Instructions (SSE)
64-Bit SIMD Integer Instructions (SSE)
Miscellaneous Instructions (SSE)
SSE2 Packed and Scalar Double-Precision Floating-Point Instructions
SSE2 Data Movement Instructions
SSE2 Packed Arithmetic Instructions
SSE2 Shuffle and Unpack Instructions
SSE2 Packed Single-Precision Floating-Point Instructions
SSE2 128-Bit SIMD Integer Instructions
SSE2 Miscellaneous Instructions
Operating System Support Instructions
64-Bit AMD Opteron Considerations
The MMX instructions enable x86 processors to perform single-instruction, multiple-data(SIMD) operations on packed byte, word, doubleword, or quadword integer operands contained in memory, in MMX registers, or in general-purpose registers.
The data transfer instructions move doubleword and quadword operands between MMX registers and between MMX registers and memory.
Table 3-20 Data Transfer Instructions (MMX)
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The conversion instructions pack and unpack bytes, words, and doublewords.
Table 3-21 Conversion Instructions (MMX)
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The packed arithmetic instructions perform packed integer arithmetic on packed byte, word, and doubleword integers.
Table 3-22 Packed Arithmetic Instructions (MMX)
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The compare instructions compare packed bytes, words, or doublewords.
Table 3-23 Comparison Instructions (MMX)
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The logical instructions perform logical operations on quadword operands.
Table 3-24 Logical Instructions (MMX)
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The shift and rotate instructions operate on packed bytes, words, doublewords, or quadwords in 64–bit operands.
Table 3-25 Shift and Rotate Instructions (MMX)
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The emms (EMMS) instruction clears the MMX state from the MMX registers.
Table 3-26 State Management Instructions (MMX)
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